Senior DFT Engineer

Hyderabad

Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore

Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market

Senior DFT Engineer

Experience: 7+ Years

Location: Hyderabad

Role Overview

We are looking for a skilled Senior DFT Engineer with 7+ years of hands-on experience in Design-for-Test (DFT) implementation for complex SoCs. The candidate will contribute to DFT architecture execution, implementation, validation, and silicon bring-up activities.

This role requires strong technical expertise in scan, ATPG, MBIST/LBIST, and production test enablement. The engineer will work closely with design, verification, product, and physical design teams to ensure high test coverage, quality silicon, and smooth production ramp-up.

Key Responsibilities

DFT Implementation & Integration

• Implement chip-level DFT solutions including:
• Scan and scan compression
• LBIST / MBIST
• Boundary Scan
• IJTAG
• Integrate DFT logic into RTL and coordinate with synthesis and physical design teams
• Support multi-clock and low-power DFT implementation

Validation & ATPG

• Validate DFT features using simulation and fault analysis
• Generate and debug ATPG patterns (Stuck-at, Transition, Path-Delay)
• Perform fault coverage analysis and drive coverage closure
• Support GLS and DFT verification activities

Silicon Bring-up & Production Support

• Support silicon bring-up activities related to scan and memory testing
• Work with Product Engineering for production test enablement
• Assist in post-silicon debug and failure diagnosis
• Contribute to yield improvement initiatives

Collaboration

• Work closely with RTL, verification, STA, power, and product teams
• Contribute to DFT methodology improvements and best practices
• Support schedule milestones and deliverables across project phases

Qualifications

Education & Experience

• BTech / MTech in Electrical, Electronics, Computer Engineering, or Computer Science
• 7+ years of hands-on DFT experience in SoC environments
• Experience in implementing and validating chip-level DFT architectures

Technical Expertise

• Strong experience in:
• Scan and Scan Compression (IP and SoC level)
• ATPG (Stuck-at, At-Speed, Transition, Path-Delay)
• Fault coverage analysis
• Hands-on experience with industry-standard DFT EDA tools (Synopsys, Cadence, Siemens/Mentor)
• Experience testing:
• Digital logic, memories, I/Os
• MBIST and/or LBIST implementations
• Good understanding of synthesis, STA, multi-clock designs, and power-aware DFT
• Exposure to ASIC implementation flows; FPGA exposure is a plus
• Familiarity with low-power architectures is desirable

Soft Skills

• Strong communication and coordination skills
• Ability to work effectively in cross-functional teams
• Strong analytical and debugging capabilities
• Detail-oriented with a quality-focused mindset
• Proactive and adaptable in dynamic project environments

Contact: Uday

Mulya Technologies

Email: muday_bhaskar@yahoo.com