Senior DFT Engineer / DFT Lead

Cadence Hyderabad is Hiring for DFT Engineer

Job Title: DFT Engineer / Senior DFT Engineer / DFT Lead

Location:

Hyderabad

Experience:

37 Years

Education:

BE/B.Tech/ME/M.Tech or equivalent degree in Electronics, Electrical, or related discipline

Job Overview

We are seeking an experienced and highly skilled Design-for-Test (DFT) Engineer to contribute to all phases of DFT architecture, development, implementation, verification, and silicon bring-up. The ideal candidate will have strong ownership, excellent technical depth, and hands-on experience in scan, ATPG, JTAG, MBIST, STA, and postsilicon validation.

Key Responsibilities

DFT Architecture, Insertion & Verification

• Implement and verify Scan, ATPG, JTAG, and MBIST architectures.
• Perform scan insertion at block level and chip top level.
• Generate, insert, and verify Memory BIST at RTL and netlist levels.
• Work on test structures, ATPG fault models, test points, and coverage improvement techniques.
• Execute gate-level simulations (GLS) with and without timing (SDF) for ATPG/MBIST/JTAG.

Tape-Out & Silicon Bring-Up

• Participate in one or more chip tape-outs, including ATE bring-up.
• Support post-silicon debug and test pattern bring-up on ATE.

Cross-Functional Collaboration

• Collaborate with design, synthesis, physical design, and STA teams to debug DFT issues.
• Ensure accurate test mode timing constraints and STA flows for block and chip.

Technical Expertise

• Strong understanding of Analog PHY and Analog Macro testing.
• Hands-on experience with JTAG standards (IEEE 1149.1 / 1149.6).
• Proficiency with industry-standard DFT tools (Cadence/Tessent preferred).
• Good scripting knowledge in Perl/Tcl for automation.

Soft Skills & Ownership

• Excellent communication skills to interact with global teams.
• Strong sense of ownership and responsibility through tape-out and post-silicon bring-up.
• Team player with the ability to collaborate and deliver in a fast-paced environment.

Required Qualifications

• B.Tech/M.Tech or equivalent with 37 years relevant DFT experience.
• Proven hands-on experience in at least one full chip tape-out.
• Expertise in Scan, ATPG, MBIST, JTAG, STA, and ATE bringup