Senior Design Verification Lead (PCIE)

Were Hiring Senior Design Verification Professionals.

Greetings from Eximietas Design...!

We are looking for experienced SoC Design Verification professionals (PCIe focus) to join our expanding global team.

Experience:

5 to 30+ Years

Locations:

India Bengaluru, Hyderabad, Pune & Ahmedabad

USA San Jose (Bay Area) & Austin

Eligibility (USA): U.S. Permanent Residents (Green Card holders).

Key Responsibilities:

• Lead SoC Design Verification for complex programs
• Develop verification strategies, test plans, testbenches & coverage models
• Verify high-speed & low-speed protocols:
• I2C / I3C, SPI, UART, GPIO, QSPI
• PCIe, Ethernet, CXL, MIPI, DDR, HBM
• Perform Gate-level simulations & power-aware verification (Xprop, UPF)
• Implement SystemVerilog assertions & functional coverage (code/toggle/functional)
• Collaborate with architects, RTL, and pre/post-silicon teams
• Ensure verification signoff with proper documentation
• Mentor junior engineers & lead verification teams
• Integrate third-party VIPs (Synopsys / Cadence)

Required Expertise:

• 5+ years hands-on SoC Design Verification experience
• Strong SystemVerilog (Assertions & Coverage) skills
• Experience with VCS (Synopsys) and Xcelium/Xsim (Cadence)
• High-speed protocol verification expertise (PCIe preferred)
• Power-aware verification using UPF
• Strong collaboration & leadership skills

Interested candidates can share resumes at: maruthiprasad.e@eximietas.design

Referrals are highly appreciated please share within your network!

Best Regards,

Maruthy Prasaad

Associate VLSI Manager Talent Acquisition | Visakhapatnam

Eximietas Design

maruthiprasad.e@eximietas.design

+91 8088969910