Senior Design Verification Engineer

Were hiring for the position of Design Verification Engineer in Bangalore and Hyderabad.

**Position:** Design Verification Engineer

**Experience:** 5+ Years

**Locations:** Bangalore & Hyderabad

**Notice Period:** Immediate Joiners Preferred

**About the Role:**

We are seeking talented Design Verification Engineers with strong experience in IP/SoC verification to join our growing semiconductor team. This role offers the opportunity to work on cutting-edge VLSI projects and collaborate with highly skilled engineering teams.

**Key Responsibilities:**

- Develop and execute verification plans for IP and SoC designs

- Build and enhance verification environments using SystemVerilog and UVM

- Perform functional verification, regression, and coverage closure

- Debug RTL and integration issues during the verification cycle

- Collaborate closely with design, architecture, and physical design teams

- Ensure high-quality deliverables within project timelines

**Required Skills:**

- 4+ years of experience in Design Verification

- Strong expertise in SystemVerilog and UVM methodology

- Experience in IP/SoC level verification

- Good understanding of industry-standard protocols such as PCIe, USB, DDR, Ethernet (added advantage)

- Knowledge of scripting languages like Python/Perl/Shell is a plus

- Strong debugging, analytical, and communication skills

Interested candidates can share their updated resumes at senthilnathan.m@univisiontechnocon.com.

Referrals are highly appreciated!