Senior Design Verification Engineer

Job Title: IP Verification Engineer (SV / UVM)

Experience: 4 15 Years

Locations: Pune | Bengaluru | Hyderabad | Chennai

Work Mode: Onsite / Hybrid

Job Summary:

Tessolve Semiconductor is looking for experienced IP Verification Engineers with strong expertise in SystemVerilog and UVM to work on verification of complex and high-performance IPs. This role offers opportunities across multiple seniority levels, including technical ownership and mentorship.

Key Responsibilities:

• Develop and maintain UVM-based verification environments for IP-level verification
• Create and execute verification plans, test scenarios, and coverage strategies
• Build SystemVerilog testbenches , sequences, drivers, monitors, and scoreboards
• Write and debug SystemVerilog Assertions (SVA)
• Perform functional, code, and coverage closure
• Debug RTL and testbench issues in collaboration with design teams
• Drive regression execution and verification sign-off
• (Senior roles) Mentor junior engineers and contribute to methodology improvements

Required Skills:

• 415 years of hands-on experience in IP Verification
• Strong proficiency in SystemVerilog and UVM
• Solid understanding of digital design fundamentals
• Experience with functional coverage and coverage closure
• Hands-on experience with simulators like VCS, Questa, or Xcelium

Preferred / Nice to Have:

• Experience verifying standard IPs (AXI/AHB/APB, PCIe, USB, DDR, Ethernet )
• Strong Assertion-Based Verification (ABV) skills
• Knowledge of low-power verification (UPF/CPF)
• Scripting skills (Python / Perl / Tcl / Shell )
• Exposure to SoC-level integration or verification

Education:

• B.E. / B.Tech / M.E. / M.Tech in Electronics, Electrical, or Computer Engineering