Senior Design Verification Engineer

Job Description

IP / SoC Verification Engineer

Experience: 815 Years

Company: Tessolve Semiconductor

Location: Chennai | Hyderabad | Bengaluru

Notice Period: 030 Days (Immediate to short joiners preferred)

Role Overview

Tessolve Semiconductor is hiring IP / SoC Verification Engineers with strong hands-on experience in functional verification of complex IPs and SoCs. This role offers opportunities to work on advanced semiconductor designs with global customers.

Key Responsibilities

• IP and SoC level functional verification
• Development and execution of SystemVerilog / UVM-based testbenches
• Creation of verification plans, test scenarios, and regressions
• Debugging of functional and integration issues
• Functional, code, and assertion coverage closure
• Collaboration with design, architecture, and validation teams
• Support verification sign-off activities

Required Skills & Experience

• 815 years of experience in IP / SoC Verification
• Strong hands-on expertise in SystemVerilog and UVM
• Solid understanding of SoC fundamentals (clocking, resets, interconnects)
• Experience with assertion-based verification (SVA)
• Strong debugging and problem-solving skills

Good to Have

• Exposure to high-speed interface protocols (PCIe, USB, DDR, MIPI, Ethernet, etc.)
• VIP integration and customization
• Low-power verification knowledge (UPF/CPF)
• Scripting skills (Python / Perl / Shell)

Why Tessolve?

• Work on cutting-edge IPs and SoCs
• Exposure to global customers and advanced technologies
• Strong learning ecosystem and career growth