Senior Design Verification Engineer

Job Title: DDR Verification Engineer

Location: Bangalore

Experience: 5+ Years

Notice Period: Immediate to 30 Days

Job Description:

We are looking for an experienced DDR Verification Engineer to join our growing verification team in Bangalore. The ideal candidate should have strong hands-on experience in DDR protocol verification and SystemVerilog/UVM-based environments.

Key Responsibilities:

• Verification of DDR (DDR3/DDR4/DDR5) IP/SoC
• Develop and execute UVM-based testbenches
• Protocol checking, assertions, and functional coverage
• Debug simulation failures and work closely with design teams
• Review verification plans and ensure coverage closure

Required Skills:

• Strong experience in DDR protocol verification
• Hands-on with SystemVerilog & UVM
• Experience with assertions (SVA) and coverage
• Good understanding of memory controller architecture
• Strong debugging and problem-solving skills

Preferred Skills:

• Experience with DDR PHY or controller verification
• Exposure to low-power features and performance verification

Location: Bangalore

Notice Period: Immediate to 30 days preferred