Senior Design Verification Engineer

Tips: UVM, Design Verification.

Responsibilities

• Senior DV engineer to develop UVM/SV-based testbench
• Good knowledge of SV/UVM is a must.
• Should have developed UVM/SV components like driver/monitor/scoreboard,
• Individual contributor role
• Exposure to protocols like AMBA, Serial protocols, PCIe, Ethernet

Qualifications

• 6 to 8 years of DV experience minimum.
• Mtech/Btech Electronics/Computer