Senior Design Verification Engineer (Europe)
Mirafra Technologies
5 - 10 years
Bengaluru
Posted: 17/12/2025
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Job Description
Must-Have:
Strong in SystemVerilog, UVM , functional coverage & constrained-random verification
Experience with Portable Stimulus / Cadence Perspec
Good understanding of digital design , MCU/SoC architectures
Hands-on with simulation & debug tools
Strong analytical and communication skills
Good to Have:
Automotive / safety-critical IC background
Knowledge of ISO 26262
Python scripting , regression automation, flow optimization
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