Senior Design Verification Engineer

We are hiring experienced ASIC Verification Engineers with strong handson expertise in SystemVerilog, UVM, and IP/SOC verification. The role involves leading a small team, defining testbench architecture, developing UVM environments, and driving coverage closure. Experience with debug tools (IUS/VCS/Questa/Verdi), scripting (Python/Perl/Shell), and protocols like AXI, PCIe, DDR, USB, CXL, Ethernet, etc., is highly preferred. Knowledge of CPU-based verification, NoC, lowpower/GLS is a plus. Strong ownership and communication skills are essential.

Experience: 6+ years

Location: Hyderabad/Bangalore/Noida/Ahmedabad/Pune/Chennai