Senior Design Verification Engineer

Key Responsibilities

• Develop and maintain SystemVerilog/UVM-based verification environments for IP/SoC-level designs
• Perform protocol-level verification for PCIe Gen 5+ and UCIe
• Define verification plans, coverage models, and test scenarios
• Develop reusable testbenches, sequences, drivers, monitors, and scoreboards
• Analyze functional coverage, debug failures, and close coverage
• Work closely with design, architecture, and validation teams to ensure protocol compliance
• Support regression execution and issue triage
• Ensure verification quality, completeness, and on-time delivery

Experience required

• 5+ years of hands-on experience in Design Verification
• Strong proficiency in SystemVerilog and UVM
• Protocol verification experience is mandatory
• Hands-on experience with PCIe Gen 5 or above
• Experience with UCIe protocol
• Excellent debugging and problem-solving skills

Educational Qualification

• B.E./B.Tech or M.E./M.Tech in Electronics / Electrical / Computer Engineering or related field