Senior Design Verification Engineer
BITSILICA
5 - 10 years
Hyderabad
Posted: 17/02/2026
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Job Description
Location : Hyderabad & Bangalore
Exp : 4 + YoE
Notice Period : 0 to 4 weeks
Job Description:
- Very strong in SV, UVM, assertions, Testbench, Testplan, coverages etc
- Should have strong knowledge on IP verification or SoC Verification or Subsystem verification
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