Senior Design Verification Engineer

Experience: 4 plus years Qualifications: B.Tech/B.E/M.Tech/M.E

Role and Responsibilities:

Candidate must have good experience in System Verilog, UVM and C based test-bench.

Expected to understand the design specification and RTL implementation, develop test-plan, tests, create verification infrastructure and verify the design.

Candidate must have good debug & amp; analytical skills.

Skill Requirements:

System Verilog, UVM methodology, C programming & exposure to scripting languages such as perl/python.

Good to have: Prior experience in IP verification