Senior Design Verification Engineer
ACL Digital
5 - 10 years
Hyderabad
Posted: 23/12/2025
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Job Description
Solid experience in SystemVerilog / UVM
PCIe protocol verification expertise
Strong understanding of IP-level protocols
Hands-on with DV environments, debugging & coverage
Ability to work across design, architecture & validation teams
#ACLDigital #HiringNow #DesignVerification #UVM #SystemVerilog #PCIe #VLSICareers #HyderabadJobs #BangaloreJobs
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