Senior Design Verification Engineer
ACL Digital
4 - 7 years
Bengaluru
Posted: 06/03/2026
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Job Description
Faulsim-Engineers
Experience : 4-7 years
Good Experience on Semiconductor/VLSI Design verification IP's.
Experience with ISO 26262 is plus
Must have Faultsim experience
Z01X tool experience and any equivalent tool
Can consider GLS experience with good verification knowledge.
Interested,please share your updated resume to janagaradha.n@acldigital.com
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