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Senior CPU Subsystem Verification Engineer

Mulya Technologies

5 - 10 years

Hyderabad

Posted: 20/02/2026

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Job Description

Hyderabad

Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore


Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market


Senior CPU Subsystem Verification Engineer

Experience: 7+ Years

Location: Hyderabad

Role Overview

We are looking for a Senior Verification Engineer specializing in CPU Subsystem and SoC-level integration verification, with strong expertise in AMBA protocol-based interconnects and full C-based CPU boot and execution flows. The role involves verifying processor clusters, coherency, memory interfaces, and system-level behavior across simulation, emulation, or FPGA platforms.

Key Responsibilities

  • Develop and own SystemVerilog/UVM + C-based verification environments for CPU subsystems
  • Verify end-to-end processor boot flows using C, assembly, or bare-metal test frameworks
  • Validate CPU interaction with AMBA-based bus architectures (AXI, AHB, APB, ACE/CHI)
  • Verify cache coherency, interrupt flows, MMU behavior, privilege modes, and low-power states
  • Debug issues across pipeline, coherency, interconnect, and memory hierarchies
  • Collaborate closely with architecture, firmware, and RTL teams to define coverage models

Minimum Qualifications

  • 7+ years in CPU or SoC subsystem verification
  • Strong understanding of AMBA protocols AXI / ACE / CHI / AHB / APB
  • Hands-on experience in C-based or assembly-based stimulus for CPU execution flows
  • Experience with SystemVerilog, UVM, and constrained-random or hybrid verification methodologies
  • Familiarity with simulation, emulation, or FPGA prototyping environments

Preferred Qualifications

  • Exposure to ARM / RISC-V / x86 pipeline and coherency verification
  • Experience in secure boot, exception handling, power/reset sequencing
  • Knowledge of cache hierarchies CHI/CXL.cache protocols
  • Understanding of performance metrics
  • Verification experience with JTAG interface


Contact: Uday

Mulya Technologies

Email: muday_bhaskar@yahoo.com

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