Senior ASIC / RTL / Logic Design Engineer

Hyderabad

Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore

Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market.

1. Senior ASIC / RTL / Logic Design Engineer Memory Controller Design 1 position preferred in Hyderabad but can be accommodated in Blr too in case of constraints.

We are seeking a highly experienced, innovative, and technically strong ASIC / RTL / Logic Design Engineer to join our Memory Controller Design Centre of Excellence (CoE). This role offers the opportunity to architect and implement highperformance memory controller IP for cuttingedge AI compute platforms powering largescale data centers and advanced machinelearning workloads.

Responsibilities

• Design and deliver standardscompliant, productionready IP blocks for DDR5, HBM4, and LPDDR6 memory controllers, optimized for AIcentric server SoCs operating at 9600 Mbps to 14400 Mbps and beyond.
• Develop architecture, microarchitecture, and detailed design specifications tailored for AI compute workloads, ensuring bestinclass performance, power efficiency, and area (PPA).
• Enhance ASIC development flows using advanced EDA tools, automation, and scripting (Python, Perl, TCL) to support rapid iteration cycles for AIfocused silicon.
• Implement complex RTL design blocks in Verilog/SystemVerilog, following robust design methodologies suitable for highbandwidth, lowlatency AI accelerators.
• Perform functional simulation, performance modeling, and debug to validate correctness and throughput under AIoriented traffic patterns.
• Demonstrate strong understanding of Lint, CDC, Synthesis, Power Analysis, STA constraints, and LEC for highfrequency, highreliability serverclass designs.
• Define and optimize timing constraints to meet aggressive frequency targets typical of AI compute architectures.
• Identify, track, and resolve design bugs across the development lifecycle using industrystandard tracking systems.
• Collaborate closely with verification, physical design, architecture, and firmware teams to ensure seamless integration into AIcentric server chip platforms.
• Participate in design reviews, code reviews, and technical discussions, driving continuous improvement in design quality and methodology.
• Mentor junior engineers, fostering a culture of technical depth, innovation, and excellence.

Key Qualifications

• B.E / M.Tech / Ph.D. in Electrical Engineering, Electronics, VLSI, or related field from a reputed institution.
• 10+ years of handson experience in ASIC design, RTL development, and logic design for complex SoCs or IP subsystems.
• Strong expertise in Verilog and SystemVerilog, with deep knowledge of digital design fundamentals, memory subsystems, and highspeed interfaces.
• Proven experience with Lint, CDC, Synthesis, Power Analysis, STA, and LEC tools (Synopsys, Cadence, Mentor).
• Experience working on serverclass, highperformance, or AIaccelerator SoCs is a strong plus.
• Excellent analytical, debugging, and problemsolving skills with the ability to thrive in a fastpaced, productfocused environment.
• Strong communication and collaboration skills for working with crossfunctional global engineering teams.

Contact: Uday

Mulya Technologies

Email: muday_bhaskar@yahoo.com