Senior ASIC Design Verification Engineer (SoC / Subsystem)

We are looking for a Senior / Principal ASIC Design Verification Engineer to lead hands-on verification of complex SoCs or large subsystems, owning execution from verification planning through tapeout and silicon correlation. This role requires deep UVM expertise and strong closure discipline.

Job Description:

• Own end-to-end verification at subsystem or SoC level, including authoring verification plans from specs and micro-architecture and building reusable UVM/SystemVerilog environments from scratch.
• Develop constrained-random and directed tests, scoreboards, checkers, coverage models, and SVA assertions to ensure functional correctness.
• Drive functional, code, and assertion coverage closure, debug complex failures, and collaborate closely with RTL, architecture, and DFT teams.
• Enable SoC-level verification covering IP/interface integration, coherency, low-power modes, resets/boot flows, and performance validation.
• Verify standard interfaces and complex subsystems such as AXI/ACE, DDR/PCIe, coherency fabrics, memory and interrupt subsystems, and power states.
• Support silicon bring-up and post-silicon correlation, leveraging scripting (Python/Tcl) and low-power or emulation exposure as value adds.

If youre seeking ownership of verification closure for silicon-critical designs and the opportunity to influence real SoC quality from pre-silicon to post-silicon, this role offers strong technical depth and impact.

Thanks,

Karthik Kumar