Senior Analog/Mixed-Signal IC Design Engineer (PLL & High-Speed SerDes)

Top15 Semicon Organization in the world

About the job

Senior Analog/Mixed-Signal IC Design Engineer (PLL & High-Speed SerDes) 412 Years Experience

About the role

This position owns the design and delivery of major analog/mixed-signal blocks spanning PLL/clocking and high-speed serial interfaces . Youll take designs from architecture through silicon validation, partnering closely with layout, validation, test, and systems teams to meet performance, quality, and schedule targets.

Job description

• Architect, design, and deliver PLL/clocking circuits (VCO, charge pump/loop filter, dividers, references, calibration) with clear phase-noise/jitter margin
• Architect, design, and deliver SerDes analog/mixed-signal blocks (TX/RX, CDR, equalization, clock distribution) with clear jitter/BER margin
• Translate system requirements into block-level specifications and make design trade-offs across jitter/phase noise, power, area, and robustness
• Run transistor-level simulations and verification across PVT corners and statistical variation; close performance with parasitic extraction
• Develop validation plans and support lab bring-up; drive sim-to-silicon correlation and root-cause isolation
• Collaborate with layout to achieve performance and yield goals; participate in design and layout reviews
• Improve design robustness (variation sensitivity, EM/IR awareness, ESD/latch-up considerations, reliability margins as applicable)
• Provide technical leadership through design reviews, risk management, and mentoring of other engineers (no direct reports required)

Minimum qualifications

• 412 years of hands-on analog/mixed-signal IC design experience with multiple successful silicon tapeouts and clear block ownership
• Strong PLL fundamentals: phase noise/jitter, loop stability, spur mechanisms, reference integrity
• Strong SerDes/high-speed fundamentals: jitter budgets, CDR behavior, equalization concepts, eye/bathtub analysis
• Expertise with SPICE simulation, debug, and device noise/mismatch fundamentals
• Experience closing performance with parasitic extraction and measurement correlation
• Strong written and verbal communication skills for cross-functional execution

Preferred qualifications

• Demonstrated measured-silicon correlation for clocking and/or high-speed interface performance targets
• Experience with mixed-signal calibration and production-oriented hooks (trim/BIST concepts, observability)
• Scripting/automation for simulation and data analysis (Python/Perl/Tcl/Matlab)

Contact:

Uday

Mulya Technologies

muday_bhaskar@yahoo.com

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