Senior Analog Mixed Signal Design Engineer (Layout)

Scope:

1. Client's Design System Qualification (concept, methodology, development)
2. The main goal is design and develop analog mixed signal designs/IPs to qualify the Client's Design Flow (set of tools and methodologies) and Design Package (DP) components (set of std cell, IO, ESD libraries, run sets, devices).
3. Execute test cases to verify the integrity of major features for flow & library interfaces, changes across various tools, methodologies, and technologies.
4. The objective is to find errors in the libraries, Device Models, Technology package, Design Flow and Design Package before they are released for productive use.

Responsibilities:

1. Design and develop analog mixed signal circuits and layouts for various applications.
2. Perform simulations to verify the functionality of analog mixed signal designs. Analyze simulation results and optimize designs as needed.
3. Perform functional verification and matching analysis to ensure design specifications are met.
4. Conduct post-layout characterization and debugging to validate performance and reliability.
5. Ensure design compliance with DRC, LVS, and ERC rules for advanced process nodes (22nm, 12nm).
6. Implement ESD protection circuit designs and perform related simulations to ensure product reliability.
7. Develop and maintain Skill scripts for layout and design automation.

Requirements:

1. At least 5 year+ of strong, hands on schematic and layout design experience.
2. Strong understanding of analog circuit design principles, device physics, and precision analog blocks (amplifiers, voltage regulators, PLLs, current mirrors)
3. Proficiency in floor-planning, placement, and routing of analog/mixed-signal circuits
4. Expert-level proficiency in Cadence Virtuoso for schematic and layout design
5. Conduct IR-drop and electromigration analysis to ensure the reliability and integrity of analog mixed signal designs
6. Expertise in Spectre, Titan, HSPICE, or AMS simulators
7. Working expertise in ESD devices, sealring, and IO PADS in analog designs