Senior Analog Layout Engineer

Hiring: Senior Analog Layout Engineer (58 Years)

Location: Kolkata / Hyderabad

Technology Node: TSMC 40nm and above

Domain: AMS (Analog Mixed Signal) Layout

We are looking for a highly skilled Senior Analog Layout Engineer with strong hands-on experience in TSMC 40nm and AMS layout design. If you have independently handled floorplanning to sign-off and successfully closed DRC/LVS on complex analog blocks this opportunity is for you.

Key Responsibilities:

Create optimized floorplans with strong focus on matching & parasitic control

Translate sub-block schematics into hierarchical layouts

Ensure 1:1 device matching with simulation hierarchy

Perform and close DRC & LVS until error-free

Ensure compliance with foundry layout rules (TSMC 40nm)

Provide extracted netlists for back-annotation

Incorporate review remarks, customer inputs & layout guidelines

Contribute improvements to Block Review documentation

Required Skills:

58 years of hands-on Analog/AMS Layout experience

Strong experience in TSMC 40nm node and above

Expertise in:

Matching techniques (Common Centroid, Interdigitation)

Guard rings, shielding, noise isolation

Parasitic-aware layout practices

Hierarchical layout methodology

DRC / LVS / Extraction flows