Senior Analog Layout

Key Responsibilities

• Would be responsible for hands-on analog routing at platform and SoC level
• Thorough knowledge of RC requirement for critical nets along with shielding implementation as per the design requirements
• Thorough knowledge of ESD requirements and integration at partition/SoC hierarchy
• Ensure quality adherence during all stages of the project life cycle. Drive thorough analysis of existing processes and recommend and implement the process improvements to ensure Zero Defect chips
• Actively work as part of team both locally & also with remote or multi-site teams

Key Skills

• Self starter with 5+ years of experience on analog IP layout and associated signal routing
• Expertise in meeting RC requirements of critical nets, shielding implementation, extraction and physical verification using Synopsys/Cadence/Mentor tools
• Sound knowledge of package type understanding, ESD integration, PI-SI analysis is desirable