RTL Release Principal Design Engineer

College education in Electronics Engineering or Computer Engineering

Exp- 7-12 Yrs

- Working knowledge in RTL design flow steps like RTL coding, Simulation, compilation/testbench validation, Synthesis, Timing, DFT,lint, CDC, LEC etc.

- Ability to debug existing Verilog/System verilog test cases with little or no help from the designer.

- Functional simulation using Verilog/System Verilog.

- Good in Scripting languages(Shell, Perl, TCL, Python) and automation of design database qualification and packaging. Checks and validation of package consistency.

- Familiarity with Power Flow (UPF/CPF).

- Able to collaborate with IP-development teams and facilitate high-quality releases.

- Maintaining package and release timelines for various projects. Time management skills enough to balance multiple high-priority projects.

- Bug reporting and resolution closure with IP providers

- Ability to debug synthesis/timing analysis constraints, reports, logs

- Ability to learn new tools/flows and develop methodology if needed.

- Ability to build and maintain close relationships with Designers and Application Engineers.

- Fastidious approach to building automated processes.

- Strong interpersonal and relationship-building skills.

Additional Desirable Qualifications:

- Familiarity with SerDes/DDR/other Design-IPs & Analog design flows

- Familiarity with IP release and tracking management systems.