RTL Design Verification Engineer

SOC RTL Design Verification

Experience: 4 to 10 Years

Location: Bangalore

Key Responsibilities:

Verification of SOC RTL (This is a DV Req) : FW-HW co-verification at SOC level, good understanding of SOC boot flow, integration level verification

Development and verification of post-si validation sequences using C/C++

Create methodology-based (UVM) verification testbenches and components from scratch at SOC level along with re-usability of IP level components.

Experienced with Verilog, System Verilog, and C or C++

Good understanding of JTAG protocol

Contributes to test plan development.

Candidate past experience requirements,

Should have experience in system-level Verification.

DDR prior experience is not mandatory.

About Company:

ACL Digital, a leader in digital engineering and transformation, is part of the ALTEN Group. At ACL Digital, we empower organizations to thrive in an AI-first world. Our expertise spans the entire technology stack, seamlessly integrating AI and data-driven solutions from Chip to cloud. By choosing ACL Digital, you gain a strategic advantage in navigating the complexities of digital transformation. Let us be your trusted partner in shaping the future.