RTL Design Engineers

About the Company

Proxelera is a specialized semiconductor design services company dedicated to accelerating silicon success by aiding engineering teams in developing high-quality ASIC/SoC designs, robust verification processes, seamless silicon-software integration. With deep expertise in VLSI, RTL design, and embedded systems development, Proxelera partners with leading semiconductor companies, OEMs, automotive engineering groups, and AI/Electronic product teams. Based on a verification-first methodology, Proxelera ensures reduced design and schedule risks while delivering predictable and flawless silicon. The company prides itself on its flexibility, deep technical capabilities, and a strong track record across industries including AI, automotive, and wireless connectivity.

Work on cutting-edge AI video processing silicon at Proxelera, building high-performance ASICs that power next-generation edge intelligence. Proxelera ODC in Bangalore is hiring 5 RTL Design Engineers to work on a cutting-edge #EdgeAIChip for #VideoProcessing.

About the Role

Experience: 510 years ONLY (strict range 4.x profiles will not be considered). Location: Bangalore (WFO 5 days/week). Notice Period: Immediate to below 60 days.

Responsibilities

• Pure #RTLDevelopment (4 positions) (No Only RTL integration-only FPGA experience not accepted)
• Real #RTLDevelopment experience
• Strong hands-on #ASICRTLCoding (Verilog / SystemVerilog)
• Experience in coding RTL blocks and/or algorithms for ASICs in Verilog/System Verilog is mandatory
• Experience in converting #Microarchitecture to #synthesizableRTLCode keeping in mind area, latency and power constraints is needed
• Solid exposure to CDC, Lint, X-prop and RTL clean-up
• Experience in running QC checks (CDC, Lint, X-prop) on the design and cleaning up design issues is mandatory
• Synthesis and constraint writing experience is good to have, but not mandatory
• Only FPGA experience not accepted
• Mixed RTL Development (Coding) + Integration (1 position) Min 2 ASIC RTL coding projects required
• Experience in coding RTL blocks and/or algorithms for ASICs in Verilog/SystemVerilog in at least 2 projects is mandatory. This candidate could also have worked on a few RTL integration projects, but mandatory experience in at least 2 ASIC RTL development (coding) projects are needed.
• 12 FPGA RTL projects are acceptable, but majority must be ASIC RTL
• Experience in running QC checks (CDC, Lint, X-prop) on the design and cleaning up design issues is mandatory
• Synthesis and constraint writing experience is good to have, not mandatory
• Only FPGA experience not accepted

Qualifications

510 years ONLY (strict range 4.x profiles will not be considered).

Required Skills

• Real #RTLDevelopment experience
• Strong hands-on #ASICRTLCoding (Verilog / SystemVerilog)
• Experience in coding RTL blocks and/or algorithms for ASICs in Verilog/System Verilog is mandatory
• Experience in converting #Microarchitecture to #synthesizableRTLCode keeping in mind area, latency and power constraints is needed
• Solid exposure to CDC, Lint, X-prop and RTL clean-up
• Experience in running QC checks (CDC, Lint, X-prop) on the design and cleaning up design issues is mandatory

Preferred Skills

• Synthesis and constraint writing experience is good to have, but not mandatory
• 12 FPGA RTL projects are acceptable, but majority must be ASIC RTL

Pay range and compensation package

Location: Bangalore (WFO 5 days/week).

Equal Opportunity Statement

Interested candidates / referrals: DM me on or share resumes at with RTL ASIC Edge AI in the subject.