We are hiring!!

Title: RTL design engineers

Job location: Bangalore (WFO)

Experience: 4 to 15 years

Immediate requirement and Quick offer and joining

what are we looking for?

*Experience in coding RTL blocks and algorithms for ASICs in Verilog/SV is mandatory

*Experience in converting Micro-architecture to synthesizable RTL code keeping in mind area, latency and power constraints is needed

*Experience in running QC checks (CDC, Lint, X-prop) on the design and cleaning up design issues is mandatory

*Synthesis and constraint writing experience is good to have, but not mandatory

Not looking for?

*FPGA RTL projects/profiles will be discounted from total experience/rejected

RTL design engineer