RTL Design
Ad Astra Consultants
2 - 5 years
Bengaluru
Posted: 29/01/2026
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Job Description
Role: RTL Designer
Experience: 4 8 Years
Location :Bangalore & Hyderabad
Job Description
- SoC / IP RTL Design Engineer with 4 8 years experience
- Expertise in writing RTL in Verilog and System Verilog
- Hands-on experience in design static checks like Lint, CDC, RDC, CLP, UPF
- Hands-on experience in integration of IP, chip IO integration
- Any candidate with PCIE/USB/Ethernet experience is good.
- Working knowledge of GIT is preferred
- Excellent analytical, and problem-solving skills
- Should have good understanding of SoC design flows
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