Principal/Senior Staff DFT Lead

Title: Principal/Senior Staff DFT Lead Engineer (India)/ Bangalore (Hybrid ) / Hyderabad (Hybrid )

Company Background

We are a well-funded US AI hardware startup building next-generation compute platforms that bring advanced, secure, and sustainable AI from the edge to the cloud. Backed by groundbreaking R&D in computation physics, ultra-efficient circuits, and scalable architectures, we are redefining whats possible in performance and energy efficiency. Join a team of industry veterans pushing the boundaries of AI and shaping technology that will serve humanity at global scale.

DFT ARCHITECTURE:

MBIST LBIST Logic Design using System Verilog/Verilog.

-Using Siemens/Mentor DFT tools to implement and verify DFT Architecture/Structures (EDT, LBIST, and SSN ,EDT, MBIST, IJTAG, 1149.1, 1149.6) in ASICs.

-Run atpg, analyze coverage, use VCS and Questa to simulate at unit & sdf.

-Perform test insertion for embedded block in SoC.

-Performing general DFT work on SoC.

-Using Cadence tools(modus) to insert/verify DFT logic.

-Some tasks in include, running ATPG to verify DFT implementation is working at block and chip level, perform fault coverage analysis, root cause low coverage issues, simulate ATPG and MBIST to verify DFT structure and patterns, work with PD to close timing on post-layout netlists, create silicon bring up plan/strategy.

-Used Siemens DFT tools to perform test insertion for embedded block in SoC.

-Used Makefile, TCL, Python to perform DFT insertion.

Contact:

Sumit S. B.

Mulya Technologies

"Mining The Knowledge Community"