Principal RTL design Engineer

About the Company

Cadence design system is Hiring for Bangalore and Hyderabad and NOIDA Engineers for Memory Controller IP R&D Team Across Cadence India Locations (Bangalore/Ahmadabad/Noida/Hyderabad).

About the Role(Principal RTL design Engineer)

Experience: 7-15 Years

Responsibilities

• Strong understanding of Advance Design Architecture
• RTL Implementation for Parametric and Configurable Design for optimal PPA
• Focused on Higher Speed and Max Performance throughput
• Working IP/SOC experience of any generic High Frequency protocols like LPDDR/DDR/HBM/GDDR/PCIe/USB/CXL will be an added advantage

Qualifications

M.Tech/B.Tech (VLSI/ECE)

Required Skills

• Strong understanding of Advance Design Architecture
• RTL Implementation for Parametric and Configurable Design for optimal PPA
• Focused on Higher Speed and Max Performance throughput

Preferred Skills

• Working IP/SOC experience of any generic High Frequency protocols like LPDDR/DDR/HBM/GDDR/PCIe/USB/CXL will be an added advantage

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