Principal Physical Design Engineer

Bangalore

About company

Top40 Semiconductor Organization in the world

Basic Qualifications

Strong academic and technical background in electrical engineering. A Bachelors degree in EE / Computer is required, and a Masters degree is preferred.
10 years experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision.
Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind!

Required Experience

Hands-on and thorough knowledge of synthesis, place and route, CTS, extraction timing analysis/STA, Physical Verification and other backend tools and methodologies for technologies 16nm or less, preferably 7nm or less.
Proven expertise in synthesis, timing closure and formal verification (equivalence) at the block and full-chip level.
Full chip or block level ownership from architecture to GDSII, driving multiple complex designs to production.
Experience with Cadence and/or Synopsys physical design tools/flows.
Familiarity and working knowledge of System Verilog/Verilog.
Experience with DFT tools and techniques.
Experience in working with IP vendors for both RTL and hard-mac blocks.
Good scripting skills in python or Perl

Preferred

Good knowledge of design for test (DFT), stuck-at and transition scan test insertion.
Familiarity with DFT test coverage and debug.
Familiarity with ECO methodologies and tools.

Contact:

Uday

Mulya Technologies

muday_bhaskar@yahoo.com

Principal Physical Design Engineer