Principal LOGIC DESIGN ENGINEER – Core Units(Front End Pipeline)

Principal LOGIC DESIGN ENGINEER Core Units(Front End Pipeline)

Fortune 100 Organization

Location: Bangalore

Introduction

As a Hardware Developer youll get to work on the systems that are driving the quantum revolution and the AI era. Join an elite team of engineering professionals who enable ourcustomers to make better decisions quicker on the most trusted hardware platform in todays market.

Your Role And Responsibilities

Lead the architecture, design and development of Processor Core Front

end of pipeline units for high-performance Systems.

• Architect and design I-Cache, Instruction Fetch, Branch Prediction and

Decode units of a high performance processor CPU

• Develop the features, present the proposed architecture in the High level

design discussions

• Estimate the overall effort to develop the feature.
• Estimate silicon area and wire usage for the feature.
• Develop micro-architecture, Design RTL, Collaborate with other Core

units, Verification, DFT, Physical design, Timing, FW, SW teams to develop

the feature

• Signoff the Pre-silicon Design that meets all the functional, area and

timing goals

• Participate in post silicon lab bring-up and validation of the hardware
• Lead a team of engineers, guide and mentor team members, represent

as Logic Design Lead in global forums.

Preferred Education

Doctorate Degree

Required Technical And Professional Expertise

12 or more years of demonstrated experience in architecting and

designing specific CPU unit(eg. I-Cache, Instruction Fetch, Branch

Prediction, Instruction Decode)

• Hands on experience of different Branch Prediction techniques
• Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core

Architecture and ISA

• Experience with high frequency, instruction pipeline designs
• At least 1 generation of Processor Core silicon bring up experience
• In depth understanding of industry microprocessor designs (e.g., x86,

ARM, or RISC-V processor designs)

• Proficiency of RTL design with Verilog or VHDL
• Knowledge of at least one object oriented or functional programming

language and scripting language.

• Nice to haves
• Knowledge of instruction decode and handling pipeline hazards
• Knowledge of verification principles and coverage
• High-level knowledge of Linux operating system
• Understanding of Agile development processes
• Experience with DevOps design methodologies and tools Required

Contact

Uday

Mulya Technologies