Principal Foundry Engineer – (Design Process Technology Co-optimization)

You will be a member of the team driving Power-Performance-Area (PPA) optimization at the most advanced process node through Design Technology Co-Optimization (DTCO) collaboration with foundries. This team works closely with Synopsys R&D and foundry partners to enhance Synopsys EDA software and improve process technology for PPA and yield.

Ideal person:

You are a highly skilled and motivated R&D Engineer with a passion for pushing the boundaries of technology. You thrive in a collaborative environment and excel at problem-solving complex issues. Your expertise in physical implementation at sub-4nm process technologies and deep understanding of advanced process technology, including finFET, GAA, and EUV, make you an invaluable asset to our team. You are eager to work closely with leading foundries and Synopsys R&D to optimize EDA engines for cutting-edge process technology. Your ability to study and enhance PPA entitlement of novel process technologies, and develop new features to push the PPA envelope, demonstrates your commitment to innovation and excellence. You are a proactive communicator, capable of providing insightful feedback on technology collaterals to improve PPA and yield.

Job role:

• Collaborating with foundries and research organizations through DTCO activities.
• Providing feedback on technology collaterals (design rules, libraries, PDK) to improve PPA of process technology under development.
• Studying the PPA entitlement of novel process technologies.
• Enhancing Synopsys tool flow and developing new features to push the PPA envelope.
• Working closely with Synopsys R&D to optimize the EDA engines for the process technology under development.
• Identifying and addressing potential issues associated with new process technology.

Skills required:

• 12+ years of relevant experience A relevant degree in electrical or computer engineering or computer science.
• 5+ years of experience in physical implementation and at sub-4nm process technologies.
• Good understanding of advanced process technology (4nm and below process nodes; finFET / GAA / EUV).
• Experience in advanced process technology development and/or enablement/DTCO/pathfinding (Plus Point).
• Solid technical understanding of the underlying concepts of IC design, implementation flow, and sign-off methodologies at advanced process nodes.