Principal DFT Engineer

Hyderabad

Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore

Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market

Job Title: Principal Engineer DFT Lead

Experience: 10+ years

Location: Hyderabad

Role Overview

We are seeking a highly skilled Principal Engineer DFT Lead to drive Design-for-Test (DFT) strategy, architecture, and execution for complex multi-chiplet SoCs. This role requires deep technical expertise in advanced DFT methodologies, strong cross-functional leadership, and end-to-end ownership of test architecture.

In this role, you will collaborate closely with design, verification, product, yield, and manufacturing teams to ensure robust, cost-effective, and high-quality test solutions. You will also gain exposure beyond traditional DFT into embedded firmware, silicon bring-up, ASIC/FPGA implementation, and post-silicon debug, making this a key leadership role across the full silicon lifecycle.

Key Responsibilities

DFT Architecture & Strategy

• Define and develop DFT methodologies for complex multi-chiplet SoCs.
• Architect and implement chip-level DFT solutions including:
• Scan and scan compression
• LBIST / MBIST
• Boundary Scan
• IJTAG
• Drive test coverage goals while optimizing for cost, performance, and quality.

Implementation & Validation

• Develop and integrate DFT logic into RTL and physical design flows.
• Ensure seamless interaction with synthesis, STA, power, and verification teams.
• Validate DFT features through simulation, ATPG, and fault coverage analysis.
• Generate and debug ATPG patterns (Stuck-at, Transition, Path-Delay).

Silicon Bring-up, Yield & Manufacturing

• Partner with Product Engineering team for silicon bring-up and production readiness.
• Enable stable and efficient scan/MBIST production testing on bench and ATE.
• Lead post-silicon debug, diagnosis, and yield improvement activities.
• Develop firmware-driven, cost-effective test strategies with built-in diagnosis for fault isolation.

Leadership & Collaboration

• Manage and mentor a team of DFT engineers, resolving complex technical challenges and meeting product schedules.
• Collaborate across global, cross-functional teams including architecture, design, verification, manufacturing, and yield.
• Promote DFT best practices and drive innovation in test methodologies.
• Build a cohesive, high-performing team capable of handling complex and evolving challenges.

Qualifications

Education & Experience

• BTech / MTech in Electrical, Electronics, Computer Engineering, or Computer Science.
• 10+ years of hands-on DFT experience in complex SoC environments.
• Proven experience creating and implementing chip-level DFT architectures.

Technical Expertise

• Strong experience with:
• Scan and Scan Compression (IP & SoC level)
• ATPG (Stuck-at, At-Speed, Transition, Path-Delay)
• Fault coverage analysis
• Expertise in EDA DFT tools (Synopsys, Cadence, Siemens/Mentor).
• Experience testing:
• Digital logic, memories, mixed-signal blocks, I/Os
• Custom LBISTs & MBISTs
• Solid understanding of synthesis, STA, power optimization, and multi-clock domain designs.
• Exposure to ASIC and FPGA flows.
• Prior experience with chiplet-based designs is a strong plus.
• Familiarity with low-power architectures.

Soft Skills & Leadership

• Strong written and verbal communication skills.
• Proven ability to coordinate across highly experienced global teams.
• Strong problem-solving mindset with attention to detail and quality.
• Can-do attitude with openness to new environments, people, and cultures.
• Ability to propose innovative, leading-edge solutions.

Contact: Uday

Mulya Technologies

Email: muday_bhaskar@yahoo.com