Principal Design Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

RESPONSIBILITIES:

Should be able to develop test plans, tests , and verification infrastructure for complex IP’s/sub-system/SOC’s.
Should be able to create verification environment using UVM methodology or any equivalent methodology.
Create reusable bus functional models, monitors, checkers, and scoreboards.
Should have experience in  functional coverage driven verification closure.


SKILL SETS:

BTech/ MTech  in Engineering

7-12years of VLSI industry experience in Verification.

Knowledge in DDR Protocol - DDR5, LPDDR5
Knowledge in USB3 protocol,
IP/Sub_System/SoC level verification experience.
Expert in developing test bench/test case using SV & UVM
Strong individual contributor and Mentorship experience

Working knowledge of verification cycle for any complex IP/SOC for atleast one/more projects.
Experience with code coverage, functional coverage & assertions is desired.
Bus protocols (AXI/AHB/APB)

Thanks

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