Principal Analog Layout Engineer

As a layout technical expert, you will be taking chip top ownership of analog-on-top ASIC developments. Looking for hands-on technical contributor, able to take chiptop ownership including tape-out procedures. A teamplayer, able to collaborate within a global layout team and cross-discipline stakeholders.

Required experience:

• 15+ years of experience in custom analog layout
• Experience with nodes in the range of 22nm-40nm-180nm is a must.
• Experience with BCD technologies is a must.
• Proven track record of owning chip top layout.
• Must be able to independently go through required tape-out procedures and take corrective actions.
• Must be able to take ownership of internal layout flows, continuously work on improvements and automation.
• Must be able to understand foundry-specific constraints and convert this to direct actions and optimize internal tape-out checklists .

Daily tasks:

• Define ASIC floorplan and perform all tape-out verifications.
• Performs layout and takes corrective actions in such a way that the final result meets all requirements as stated in the Design document, conform to standard layout practices, conform to foundry layout rules, including all remarks from review, the customer and back annotation.
• Performs DRC and takes corrective actions if needed until DRC is error free
• Performs LVS and takes corrective actions if needed until result is successful
• Support the layout engineering team in handling complex layout issues.
• Follow tape-out procedures for chip top sign-off and deliver final GDS to the foundry.
• Must remain in contact with the foundry to efficiently find solutions to new challenges.

Interested in applying or know someone who would be a great fit? Please share the profile at ranjith.allam@cyient.com