Pre-silicon - Analog And Reliability Validation Engineer

Hiring: PreSilicon Analog IP Validation Engineer (34 yrs | Bangalore)

Were looking for a talented engineer to join our team and work on cuttingedge Analog IP validation for nextgen SoCs.

(Design Enablement | Analog Simulation | Reliability Validation)

Were looking for an engineer passionate about presilicon analog IP validation and simulationbased design enablement for nextgeneration SoCs.

This role is entirely simulationdriven no postsilicon or software validation.

Role Overview 100% PreSilicon Simulation

As part of our Design Enablement (DE) team, you will validate Analog IPs at schematic and postlayout stages using industrystandard SPICE tools.

What Youll Work On

• Presilicon validation of Analog IPs (opamps, current mirrors, LDOs, references, ADCs/DACs, etc.)
• Running functional, structural, and reliability (HCI/BTI) simulations
• Working in Cadence Virtuoso environment for schematic + testbench development
• SPICEbased simulation using Spectre, FineSim, AFS
• Postlayout validation including PEX extraction and corner simulations
• Debugging analog behavior & collaborating with designers for fix recommendations
• Supporting SoC teams with integrationlevel presilicon validation

Required Skills

• 34 years experience in analog IP validation or analog circuit design
• Strong fundamentals in analog circuits (opamps, references, regulators, dataconverters)
• Handson with Virtuoso, Spectre/FineSim/AFS, and SPICElevel analysis
• Experience with aging models (HCI, BTI) & reliability simulations
• Knowledge of parasitic extraction (PEX) and postlayout simulations
• Ability to build analog verification testbenches and run simulation regressions
• B.Tech/M.Tech in Electronics or related fields

Think youre a fit? Lets connect!