Post silicon Validation

Role: Post Silicon Validation Engineer(RTL Design, FPGA Design)

Experience: 5 8 years

Location: Hyderabad, On-site

Notice Period: Immediate Joiners

Responsibilities:

FPGA Design Flow & Validation

RTL Design, Implementation, and Protocols (PCIe, Ethernet, DDR4/5, Memory)

Integration-focused role: 80% Integration, 20% Design

System-level Testing & Design

Silicon Validation

Debugging Interfaces and Design-level Debugging

Board-level Debugging

Requirements:

Strong knowledge in RTL design and implementation

Expertise in FPGA design flow and validation

Experience with system-level testing and silicon validation

Hands-on exposure to debugging (board level & design level)

Familiarity with Xilinx / Intel toolchains

Understanding of protocols: PCIe, Ethernet, DDR4/5, Memory

Please share your Relevant profiles or refer your friends or colleagues to jhansi.bv@leadsoc.com for further discussion.