Physical Design Lead - Semiconductors

Physical Design Lead | Experience: 15+ years | Location: Bangalore or Hyderabad

We are seeking an experienced Physical Design Lead to oversee and drive all PD projects across Cyient Semiconductors. The ideal candidate will have a strong track record of managing large teams, delivering complex chips to tape-out, and guiding all stages of the physical design flow. This role requires deep technical expertise, strong leadership, and the ability to ensure high-quality, on-time project execution.

Key Responsibilities

• Lead and manage all Physical Design (PD) projects across multiple teams and sites.
• Oversee end-to-end PD activities including floorplanning, power planning, clock tree synthesis, place-and-route, and timing closure.
• Drive chip-level and block-level sign-off for timing, power, IR drop, EM, and DRC/LVS.
• Collaborate closely with RTL, Architecture, Verification, and Packaging teams for seamless integration.
• Review project schedules, allocate resources, and ensure delivery within timelines and quality targets.
• Mentor and guide large teams, providing technical direction and best practices.
• Resolve complex design challenges and optimize for PPA (Power, Performance, Area).

Required Skills & Qualifications

• 15+ years of hands-on experience in Physical Design for complex ASICs/SoCs.
• Strong expertise in floorplanning, PnR, clock tree synthesis, STA, timing closure, and sign-off methodologies.
• Solid understanding of advanced technology nodes (7nm/5nm/3nm preferred).
• Proficiency with EDA tools such as Synopsys ICC2, Fusion Compiler, Cadence Innovus, PrimeTime, and Voltus/RedHawk.
• Experience managing and mentoring large PD teams and leading multi-site execution.
• Strong analytical, problem-solving, and debugging skills.
• Excellent communication, stakeholder management, and leadership capabilities.