Physical Design & Implementation Engineer

Responsibilities:

1. Independently handling Block level PnR implementation with industry-standard tools.
2. Perform physical design tasks, including Synthesis, floorplanning, placement, routing, and optimization, to create high-performance, low-power designs that meet project requirements.
3. Responsible for Clock Tree Synthesis, Physical Verification (DRC and LVS), and taking blocks to closure.
4. Ownership of digital sub-blocks/chip level (specification and implementation).
5. Definition of new test cases similar to product definition and for designing significant blocks of chip, including chip architecture and chip top integration, with a focus on improving Quality of Design System.
6. Responsibility for the setup and running of test cases, analyzing failures, and bug fix validation and verification by analyzing all device models/components in the technology and ensuring ~100% coverage in the test plan/test cases.

Requirements

1. Strong understanding of the RTL2GDSII flow or design implementation in leading process technologies.
2. Must have hands-on experience in all stages of design synthesis, floor planning, placement, CTS, routing, crosstalk avoidance, and physical verification.
3. Experience with Calibre LVS, DRC issues, and closing blocks with DRC and LVS clean.
4. Strong knowledge and experience in standard place and route flows; FC/Synopsys and Innovus/Cadence flows preferred.
5. Good understanding of timing concepts knows how to handle setup/ hold violation, STA, and timing closure.
6. Must have knowledge of Physical verification, Extraction, SDF generation, PrimeTime, Multi-mode multi-corner optimization, EM/IR drop analysis, and low power techniques (UPF knowledge).
7. Block level PnR implementation in technologies with feature sizes of 90nm, 65nm, 40nm, 22nm, and 12nm or lower technology nodes.