Physical Design -Head

We are looking for a Physical Design leader who has delivered complex SoCs at advanced nodes and understands what it takes to take silicon from concept to GDS without drama. This role demands technical depth, execution maturity, and the ability to build and scale strong PD teams.

The Mandate

Drive full-chip physical design from floorplan to tapeout

Architect power, clocking, and floorplan strategy for high-performance SoCs

Lead timing closure across multi-mode, multi-corner scenarios

Own PPA convergence across advanced nodes (7nm / 5nm / 3nm preferred)

Oversee physical verification and signoff (DRC, LVS, IR/EM, noise, reliability)

Define and refine PD methodology, flows, and automation

Partner with RTL, STA, DFT, and architecture teams to ensure physical feasibility

Mentor senior engineers and build a high-output PD organization

The Profile

14+ years in ASIC Physical Design with multiple successful tapeouts

Strong expertise in ICC2 / Fusion Compiler / Innovus / PrimeTime

Deep understanding of timing, SI/PI, and high-frequency design challenges

Strong scripting ability (Tcl / Python / Perl)

Experience in CPU, GPU, AI, or HPC-class silicon preferred

Exposure to chiplet / multi-die environments is a plus

This is a silicon ownership role. Strategy plus execution.

Cheers,

Shahid