Company:Global Technology organization

Key Skills: Physical Design, Placement, Floor Planning, Routing, Cadence Innovus, Static Timing Analysis, Clock Tree Synthesis

Roles and Responsibilities:

Define and implement physical design for SoCs at both block and top levels, including floor planning and partitioning strategies.
Perform placement and routing (P&R) to achieve timing, congestion, and power targets.
Collaborate with micro-architecture and RTL teams to conduct feasibility analysis and optimize PPA trade-offs.
Develop and refine physical design methodologies and implementation flows across various stages of the design cycle.
Drive timing closure through detailed static timing analysis and constraint optimization.
Implement clock tree synthesis strategies to achieve skew, latency, and power targets.
Execute and analyze signoff flows including timing, power, EM/IR, and physical design verification.
Utilize scripting languages such as Unix shell, Perl, Python, and TCL to automate and enhance design processes.
Manage multiple tape-outs in deep submicron technologies (7nm and below) while adhering to aggressive schedules.
Communicate effectively within cross-functional engineering teams to resolve complex design challenges.

Skills Required:

Strong hands-on experience in physical design including floor planning, placement, and routing.
Expertise in static timing analysis and timing closure methodologies.
Experience with clock tree synthesis and power optimization techniques.
Proficiency in Cadence Innovus or similar place-and-route tools.
Strong understanding of deep submicron design challenges and PPA optimization.
Experience running signoff checks including timing, power, and EM/IR analysis.
Proficiency in scripting using TCL, Perl, Python, or Unix shell for automation.
Ability to manage complex SoC designs across advanced technology nodes.
Strong analytical and problem-solving skills in semiconductor design environments.

Education: Bachelor's or Master's degree in Electrical Engineering with significant experience in physical design and advanced technology nodes.

Physical Design Engineer_96212