Physical Design Engineer

Full Chip Physical Design Engineer

Job Summary:

We are seeking a highly motivated and skilled engineer to join our SoC implementation team. You will be responsible for the physical design of complex ASICs and SoCs, working on full-chip floorplanning, integration, and signoff activities to meet aggressive PPA (Power, Performance, Area) goals.

Key Responsibilities:

• Drive full chip-level physical design flow from RTL to GDSII.
• Ownership of chip-level floorplanning, partitioning, and integration.
• Collaborate with RTL, synthesis, DFT, and STA teams to resolve cross-functional issues.
• Implement place & route flows including timing closure, IR/EM, and congestion optimization.
• Perform physical verification (LVS/DRC/ERC) and work with foundries to fix violations.
• Manage static timing analysis (STA) at top level and work closely with timing owners for signoff.
• Handle power planning and power domain implementation (UPF/CPF-based).
• Contribute to methodology improvements and automation.

Required Qualifications:

• Bachelor's or Masters degree in Electrical/Electronics/Computer Engineering or related field.
• 36 years of experience in physical design with at least one full chip tapeout.
• Hands-on expertise with industry-standard tools such as Synopsys (ICC2, Fusion Compiler, PrimeTime), Cadence (Innovus), and Mentor (Calibre).
• Strong knowledge of physical design concepts: floorplanning, CTS, routing, timing closure, IR drop, EM, DRC/LVS.
• Proficiency in scripting languages like Tcl, Perl, Python, or Shell.
• Familiarity with hierarchical design and ECO flows.

Experience: 3 to 6 Years.

Location: Bangalore / Hyderabad .

Notice Period: Less than 30 days