Job Description

Role/Skill: Physical Design Engineer Lead

Experience: 8+

Location: Hyderabad/Bangalore

Key Responsibilities:

Own and drive floorplanning for complex SoC or IP blocks from RTL to GDSII.
Collaborate with RTL, DFT, and architecture teams to understand design requirements and translate them into optimal floorplans.
Perform macro placement, power grid planning, pin placement, and block-level partitioning.
Analyse and optimize for congestion, timing, area, and power.
FEV debug and closure.
CLP sign-off.
Low power optimisation and UPF development.
Work closely with place & route, clock tree synthesis, and timing closure teams to ensure floorplan quality.
STA sign-off.
IR drop analysis and EM verification.
Physical verification sign-off.

Required Skills:

Strong hands-on experience with EDA tools like Cadence Innovus, Synopsys ICC2, or Mentor Olympus.
Deep understanding of physical design flow, especially floorplanning, placement, routing, and STA.
Experience in hierarchical design, multi-voltage domains, and power planning.
Good knowledge of timing analysis, signal integrity, and DFT-aware floorplanning.
Proficiency in scripting (Tcl, Perl, Python) for automation and debugging.
Familiarity with Physical verification tools such as Calibre

Physical Design Engineer