Physical Design Engineer
ACL Digital
2 - 5 years
Hyderabad
Posted: 29/01/2026
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Job Description
PDN Engineers
Experience : 2+ years
Location : Hyderabad & Bangalore
- IR Signoff CPU/high performance cores
- Signal EM & Power EM Signoff for Chip TOP level & Block level CPU/DSP and other HMs
- Development of PG Grid spec for different HM
- Validating the PG Grid using Grid Resistance & Secondary PG Resistance Checks
- Validating the IR Drops using Static IR , Dynamic IR Vless & VCD Checks for validating Die & Pkg Components of IR Drops
- Working with SOC and Packaging Teams on Bumps Assignments / RDL Enablement / Pkg Routing Optimizations to improve overall PDN Design
- Good knowledge on PD would is desirable.
- Python , Perl , TCL
- Skills
- Hands on experience in PDN Signoff using Redhawk / RHSC / Voltus at block level / SOC Level.
- Good understanding on Power Integrity Signoff Checks.
- Proficient in scripting languages (Tcl and Perl).
- Familiarity with Innovus for RDL / Bump Planning/PG eco.
- Ability to communicate effectively with multiple global cross-functional teams.
- Tools : Redhawk , Redhawk_SC and basic use case of Innovus/ Fusion Compiler
- Power Planning/Floor planning ,Physical Verification hands on experience is added advantage.
LSF /compute optimization understanding.
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