Job Details:

Job Description:

Join Intel and Shape the Future of Computing Technology
As a Technical Manager, you will lead a team of Quality Assurance (QA) engineers in validating Process Design Kits (PDKs) for design components across various process nodes and EDA flows. PDKs are crucial for modeling, implementing, and verifying Intel's products before manufacturing. You'll be part of the Design Technology Platform (DTP) organization, collaborating with teams in the United States, India, and Malaysia to build a world-class PDK QA team.

Key Responsibilities:

Lead the development and execution of regression test suites to validate PDKs, focusing on Runset/Design Rules Verification, Parasitic Extraction, Fill, PERC ESD, and Reliability Verification (RV) across multiple process nodes and EDA tools.
Develop targeted test cases, adopt customer IP as test cases, automate regression runs, debug failures, and collaborate with PDK developers to resolve issues before release.
Oversee root cause analysis for design issues related to specific process technologies and drive initiatives to enhance design methodologies for high-quality solutions.
Manage internal and external stakeholders to ensure effective collaboration and project delivery.
Oversee both people and technical deliverables within the PDK QA team.
Report monthly progress on OKRs and execution status to higher management.
Conduct performance reviews, assess skills, provide coaching, and support employee development.
Enable teams to execute through clear goal setting, facilitating work, maintaining accountability, and driving team results.
Inspire and develop team members, role model Intel values, and ensure a productive work environment.

#designenablement

Qualifications:

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Requirements:

Bachelor's degree with 12+ years of experience, or a Master's degree with 10+ years of experience in the PDK domain.
Proven experience in PDK development, QA, and/or customer support.
In-depth knowledge of PDK layout and back-end flows, including layout verification rule decks, parasitic extraction, DFM flows, PERC ESD, and reliability verification.
Familiarity with a range of EDA tools from various vendors.
Strong planning, prioritization, and delegation skills.
Excellent verbal and written communication skills.

Preferred Qualifications:

Some experience in analog design.
Demonstrated leadership and team management experience.
Ability to collaborate effectively with cross-functional teams.
Strong problem-solving skills and a proactive approach to challenges.

#DesignEnablement

Job Type:

Experienced Hire

Shift:

Shift 1 (Malaysia)

Primary Location:

Malaysia, Penang

Additional Locations:

Business group:

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

PDK QA Manager

intel

Job Description