Job Description

Function: IP Regression Digital Design Methodology Engineer

Grading: External/Consultant

General Information

General Purpose/

Objectives:

Enable IFX SoC/IP projects onboard with automation methodology from Hardware Perspective.

Major Tasks and Activities:

General

Innovation in Automating ASIC Design Flows: Apply best-in class automation methodology in CAD VLSI domain to achieve faster time to market.
Support Design Teams: Supporting IP/SoC development teams with the rollout of IP-Regression automation, by troubleshooting design issues (synthesis and other downstream design steps)
Collaborate Cross-Functionally: Work closely with design, verification, and software teams to integrate automation solutions and ensure seamless flow implementation.
Troubleshoot and Improve: Identify bottlenecks and troubleshoot issues in the design flow, implementing solutions to enhance overall efficiency.
Develop Automation Tools: Create and maintain scripts and tools using languages like Perl, or Tcl to automate tasks, reducing manual effort and errors.

Qualification

Education: Bachelor's or Masters degree in Electronics/Electrical Engineering, Computer Science, or a related field.
Experience: 3+ years in VLSI Frontend design, with a focus on automation.
Mandatory: Strong hands-on experience with Logic Synthesis tools (Fusion Compiler/DC-NXT, Genus, Innovus)
Desired: Basic concept of PnR
Mandatory: Proficiency in HDLs (any one of VHDL, Verilog, System Verilog)
Desired: Knowledge of scripting/programming in Python/Perl/TCL etc.
Soft Skills: Strong problem-solving abilities, excellent communication, and teamwork skills.

Interested candidates, share resume at sayantikamajumdar@mirafra.com.

PD CAD (QA Regression) Engineer