PCIE Verification Engineer

Hiring PCIe Gen5/6/7 DV Engineers | 5+ yrs | Bangalore | Immediate joiners preferred

JD:-

Hiring: PCIe Gen5/6/7 Verification Engineer | Bangalore

We are looking for highly skilled PCIe Verification Engineers with 5+ years of experience to join our growing team in Bangalore. This is an exciting opportunity to work on cutting-edge high-speed protocols (Gen5/Gen6/Gen7) in advanced SoC environments.

Key Responsibilities:

• Develop and execute verification plans for PCIe Gen5/6/7 IP/SoC
• Build and enhance UVM/SystemVerilog-based verification environments
• Work on end-to-end protocol verification including LTSSM, TLP, DLLP layers
• Debug complex issues using waveforms, logs, and protocol analyzers
• Develop testcases, checkers, assertions, and coverage models
• Drive functional and code coverage closure
• Collaborate with design, architecture, and validation teams

Required Skills:

• Strong experience in SystemVerilog & UVM
• Deep understanding of PCIe protocol (Gen5/Gen6; Gen7 is a plus)
• Hands-on with protocol debugging, compliance, and performance verification
• Experience with assertions (SVA), coverage-driven verification
• Good exposure to SoC/Subsystem level verification
• Strong debugging skills with waveforms and simulations

Good to Have:

• Experience with high-speed interfaces (DDR, Ethernet, CXL, etc.)
• Exposure to emulation or FPGA-based verification
• Knowledge of low power verification (UPF/CPF)
• Scripting skills (Python/Shell)

Job Details:

Location: Bangalore

Experience: 5+ years

Notice Period: Immediate to 60 days preferred