PCIe/DDR/Ethernet Verification Engineer

Scaledge Technology is Hiring: Senior Design Verification Engineer with 4+ yrs of experience!

Were looking for a Senior DV Engineer with strong hands-on experience in System Verilog & UVM.

4+ years in Design Verification

UVM, SV, functional coverage, assertions

Any high speed Protocol exposure ( PCIe /Ethernet/USB / DDR )

Strong debug & collaboration skills

Location: Bangalore

Please share updated resume on erum@scaledge.io