NPU Processor Synthesis Technical Lead - Design Implementation

Hiring: NPU Synthesis Lead Bangalore (15+ yrs)

Were looking for an experienced NPU Synthesis Lead to drive RTLSynthesisTiming closure for NPU IP/subsystems in advanced SoCs, optimize PPA, and partner closely with RTL/STA/PD teams to deliver highquality netlists on cuttingedge nodes.

Queries: veenb@qti.qualcomm.com

Key Responsibilities

• Own RTLtogate synthesis for NPU IP/subsystems; build & maintain synthesis scripts/flows
• Lead pre/postlayout timing closure across corners; partner with STA to resolve setup/hold
• Drive physicalaware synthesis and lowpower strategies (UPF/CPF) for aggressive PPA targets
• Manage SDC constraints (clocks, I/O, MCP, false paths)
• Perform LEC, CLP, lint, and flow QoR checks; mentor junior engineers

Mandatory Skills (MustHave)

• 15+ years in ASIC synthesis & timing closure; 3+ years with NPU/AI/DSP cores
• Strong ASIC flow knowledge: RTL Synthesis STA P&R
• Handson with Synopsys Design Compiler / Cadence Genus and PrimeTime
• Proven lowpower design with UPF/CPF, multivoltage experience
• Advanced scripting: Tcl/Perl/Python for automation
• Familiarity with Spyglass/Lint/CDC and power analysis tools
• Team leadership and crossfunctional coordination (RTL/DFT/PD/Arch)

Good to Have

• Advanced nodes (5nm/3nm), hierarchical & physicalaware flows
• Tapeout experience for NPU or highperformance DSP cores