Memory Layout Engineer

Prodapt is the largest specialized player in the Connectedness industry. As an AI-first strategic technology partner, Prodapt provides consulting, business reengineering, and managed services for the largest telecom and tech enterprises building networks and digital experiences of tomorrow. Prodapt has been recognized by Gartner as a Large, Telecom-Native, Regional IT Service Provider. A Great Place To Work Certified company, Prodapt employs over 6,000 technology and domain experts in 30+ countries. Prodapt is part of the 130-year-old business conglomerate The Jhaver Group, which employs over 32,000 people across 80+ locations globally.

Job Description:

• Responsible for custom layout design of memory blocks (SRAM, DRAM, ROM, Register Files, etc.)
• Perform DRC/LVS checks, parasitic extraction, and layout optimization
• Collaborate closely with circuit design teams to ensure performance, area, and reliability targets are met
• Hands-on experience in Cadence Virtuoso, Calibre/Assura, and deep submicron/FinFET technologies preferred (2nm to 7nm TSMC)